High-Order Delayed Signal Cancellation-Based PLL Under Harmonically Distorted Grid Voltages

Quasi type-1 phase-locked loop (QT1-PLL) has become very popular in recent times for grid-connected converters owing to their simple structure and fast dynamic response. By means of the use of a half-cycle moving average filter (MAF), this PLL can completely eliminate all the nominal frequency odd-order harmonics. However, the performance deteriorates when the grid experiences frequency drift. To address this issue, high-order nonadaptive MAF with the same window length has been proposed in the literature. Although it improves the off-nominal frequency performance, the filtering-induced phase-lag remains the same. To address this issue, high-order delayed signal cancellation (DSC) technique is considered in this study. The proposed technique demonstrates similar filtering performance as high-order MAF, however, by using lower window length. This makes the proposed technique fast responsive with lower memory requirement compared to similar other techniques in the literature. Detailed small-signal modeling and associated parameter tuning method are established to facilitate the implementation of the proposed method inside current controllers of grid-connected converters. Comparative experimental results are provided with QT1-PLL and third-order QT1-PLL (TQT1-PLL) to illustrate the suitability and performance enhancement by the proposed method. These results show that in addition to the superior filtering capability of the proposed PLL, its settling time is less than one cycle of nominal frequency under most grid conditions. Consequently, in terms of enhancing the dynamic response of the QT1-PLL, the proposed HDSC-PLL is superior to the TQT1-PLL.